The invention relates to a circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns for testing semiconductor memories.
A circuit arrangement of this type is known from the publication with the title "A 60-ns 3.3-V-Only 16-Mbit Dram with Multipurpose Register" by K. Arimoto et al. (Mitsubishi Electric Corporation) in the IEEE Journal of Solid-State Circuits, Vol. 24, No. 5, October 1989 (page 1184 to 1190). This arrangement comprises a circuit arrangement for a parallel line-mode-test (LMT), in which random bit patterns are written into a multi-purpose register (MPR) and into memory cells, the bit patterns read out of these memory cells are compared in comparator circuits with the bit patterns of the MPR and the signals from the comparator output are combined by a wired-OR logic connection, in order to switch the addressed word line over to a back-up word line (redundancy) in the event of a fault.